AMD Describes Quad-Core Design

K8L, as it's called, is AMD's quad-core baby. Ars Technica has the lowdown on some of the features the chip will contain, including 128-bit floating-point and SSE units, improved branch prediction, dedicated stack engine, and memory disambiguation. The four cores will share 2MB of L3 cache, and each core had a dedicated 512KB L2 and 64KB L1 cache.

"Let's take core architecture first, because it's the one that's most familiar from past Intel-AMD comparisons. Note that I'm taking a preliminary stab at comparing these two architectures, and that my knowledge of K8L isn't nearly as thorough as my knowledge of Core. So I reserve the right to change my opinion once I get more details about AMD's new architecture. (If anyone at AMD wants to send me an optimization manual or a whitepaper, feel free.)"
Tags:  AMD, Core, quad-core, Design, sig, IGN, AM